Formation of nFET and pFET devices on a wafer requires complicated semiconductor fabrication processes. For example, patterning of an nFET and pFET on a single wafer requires two masking and lithography steps, followed by separate etching processes, e.g., reactive ion etching (RIE). These separate masking steps add significant time and cost to the manufacturing process.
In addition, it is very difficult to align two separate masks for the nFET and pFET devices. The misalignment of the masks results in a gap between such misaligned masks. Due to misalignment of the masks (gap), subsequent etching steps create a bump between the nFET and pFET. This bump, in turn, causes complications in downstream fabrication processes. For example, due to the bump, complicated fabrication processes are required in replacement metal gate processes to open the poly. These complicated fabrication processes also add significant time and cost to the manufacturing process.